Clock generation for digital systems generally requires clock frequencies that are stable, and in many cases the digital system clock frequencies are related by integer multiples. Typically, the master clock starts as the output of a crystal-controlled oscillator, and then various shaping circuits generate a digital version of the oscillator output. These shaping circuits provide fast rise and fall times as well as symmetry between the two halves of the clock period.
Many times, a phase lock loop (PLL) is used with a voltage-controlled oscillator (VCO) in a feedback loop to generate a high frequency clock from a lower frequency clock. In this way, the stable master clock is of a lower frequency that may be easier to generate. More specifically, the PLL may employ a VCO and a phase detector. The stable, lower frequency clock is input into the PLL circuit as a reference clock. The phase detector compares the phase of the reference clock with the phase of a feedback clock signal having a comparable frequency. The feedback clock is the clock signal output by the PLL but divided to be the frequency of the reference clock if the frequency of the output is correct. When the frequency or phase of the feedback clock is different from the reference clock, the voltage applied to the VCO is varied, increasing or decreasing the phase/frequency output by the VCO based upon the difference between the reference clock and the feedback clock signals.
VCOs are commonly implemented using one or more integrated circuits (ICs) in topologies such as a ring oscillator topology. The ring oscillator topology provides a series of cascaded delay stages, where the output signal from the last delay stage is fed back to the input of the first delay stage. Total delay through the cascaded stages (plus any net inversion of the signal within the system) is designed to satisfy criteria for sustained oscillation. Typically each delay stage has a variable delay governed by an independent input, and oscillation frequency is controlled using such input to vary stage delay. The oscillation frequency for a ring counter can be tuned over a fairly wide range, perhaps 20% to 50% of the nominal center frequency.
With the output frequency of the VCO being divided for comparison with the reference clock, the frequency of the signal output by the PLL circuit can be higher than the frequency of the reference clock. However, generating a high frequency signal with a VCO in this manner is limiting because VCOs can only generate certain frequency ranges and the internal frequencies utilized by conventional processors and data transmission systems are approaching those limits. Further, operation of the VCOs at high frequencies, approaching the physical limitations of VCOs, consumes a significant amount of power.
There is, therefore, a need for a way to generate high frequency clock signals using a VCO and to operate the VCO at a lower frequency to conserve power.